1. Field of the Invention
The present invention relates to a field effect transistor structures and, more particularly, to a field effect transistor structures with a multi-layered gate electrode structures and process of making same.
2. Background and Related Art
Various types of integrated circuits are fabricated on semiconductor substrates and p-channel type field effect transistors and n-type field effect transistors are major circuit components of the integrated circuits. The desire for increased speed and density, however, has resulted smaller and smaller gate electrodes and extremely thin gate insulating layers. This has, in turn, resulted in what has been called the “short channel” effect which tends to occur in field effect transistors due to narrow gate widths.
One solution to the problem of “short channel” effect has been the introduction of dopant impurity, opposite to the channel conductivity, into the gate electrode. Boron, for example, is introduced into the polysilicon gate electrodes of p-channel type field effect transistors (pFETs) and arsenic or phosphorous is introduced into the polysilicon gate electrodes of n-channel type field effect transistors (nFETS).
Although this solution is effective in overcoming the “short channel” effect problem, it has manifested at least one other problem in its effective implementation. This problem is centered on the fact that the thermal energy required for activation of dopant impurity is very difficult to adjust. If the thermal energy is large, most of boron dopants in the gate electrode is fully activated. However, because the diffusivity of boron in silicon is high, atomic boron penetrates through gate insulating layer into the Si-channel. As a result, this created another short channel effect problem. On the other hand, if the thermal energy is not sufficient, boron dopant is partially activated, leaving a considerable amount of boron inactive at the boundary between the gate insulating layer and gate electrode. This creates electron depletion affecting, in turn, the integrity of the threshold of the gate.
A solution to this latter problem has been found by introducing germanium into the structure. This has been implemented in the prior art in a boron-doped multi-layered structure by including a layer of silicon-germanium (SiGe). Thus, multi-layered gate structures may comprise, for example, an amorphous silicon layer on the gate insulating layer and a SiGe layer laminated on the amorphous silicon layer. A polysilicon layer is, in turn, laminated on the SiGe layer and a cobalt silicide layer is then formed in self-aligned manner on the polysilicon layer. The germanium in the SiGe layer is thought to enhance activation of the boron doped in the silicon thereby reducing, or possibly eliminating, the amount of inactive boron and the resulting gate electrode depletion. Such an arrangement has been described in U.S. Patent Application Publication US2003/0049919A1.
Regardless of the mechanism, the electrically active concentration of boron in the SiGe polycrystalline multi-layer gate electrode structure has been demonstrated to significantly reduce gate electrode depletion in pFETs. For simplicity of integration, it is advantageous to use the same SiGe polycrystalline multi-layer electrode structure on nFETs doped with arsenic or phosphorous. However, it has been found that the high Ge concentration in the polysilicon results in very poor CoSi2 formation on the gate structures, and particularly on the nFET gate structures.
The poor CoSi2 formation has been attributed to the fact that the Ge diffusion coefficient in the SiGe alloy through poly-grain boundaries is extremely high. Because of the large thermal energy employed in CMOS integration, the Ge is up-diffused and achieves equilibrium through the poly gate. Therefore, poly-silicide formation of the poly-SiGe alloy gate and metal cobalt is practically impossible since cobalt is unreactive chemically with the element Ge. This results in, at best, in a coagulated and discontinuous layer of CoSi2 on the poly-SiGe alloy gate. The end result is a high resistive gate. On the other hand, the element Ge is also known to have a high surface energy and, thus, the SiGe alloy material is extremely difficult to be made to chemically absorb on the gate dielectric structure of multi-layer polysilicon gate structures. In this regard, poly-SiGe alloy gate structures with low Ge concentrations can be formed on gate insulating layers. However, as Ge concentration is increased up to around 20% and above, SiGe alloy becomes discontinuous.